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data sheet mos integr a ted circuit m pd6376 audio 2-channel 16-bit d/a converter the m pd6376 is an audio 2-channel 16-bit d/a converter. the m pd6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset, and low power consumption by using the cmos process. it operates on a single 5-v power supply, and it is pin- compatible with the m pd6372 when pin 1 is low level or open. features ? single 5-v power supply ? cmos structure ? on-chip output operational amplifier circuit ? on-chip 0-point offset circuit ? resistor string configuration ? 8 f s (2 ch 400 khz) supported ? on-chip 2-channel dac ? l-r in-phase output ordering information part number package m pd6376gs 16-pin plastic sop (300 mil) the information in this document is subject to change without notice. the mark shows major revised points. document no. s12799ej5v0ds00 (5th edition) (previous no. ic-2531) date published december 1997 n printed in japan 1991
m pd6376 2 block diagram 13 14 15 16 1 2 3451278 9 6 11 10 lrck/wdck lrsel/rsi si/lsi clk d.gnd nc a.gnd r.ref r.out l.out l.ref analog power supply block digital power supply block main dac main dac sub dac shift register latch timing generator sub dac d.v dd a.v dd 4/8 f s sel
m pd6376 3 pin configuration (top view) 16-pin plastic sop (300 mil) 1 2 3 4 5 6 7 8 clk si/lsi lrsel/rsi lrck/wdck a.gnd l.out l.ref r.ref 16 15 14 13 12 11 10 9 4/8 f s sel d.gnd nc d.v dd a.gnd r.out a.v dd a.v dd
m pd6376 4 1. pin functions pin no. symbol name i/o function 1 4/8 f s sel input when this pin is low or leaves open, l-ch data and r-ch data is input in time-division from pin 15. when this pin is high, l-ch data is input from pin 15, and r-ch data is input from pin 14. (pulled down in ic with 100-k w resistor) 2 d.gnd digital gnd CC gnd pin of logic block 3 nc non connection CC not connected to internal chip 4 d.v dd digital v dd CC power supply pin to logic block 5 a.gnd analog gnd CC gnd pin to analog block 6 r.out r-ch output output right analog signal output pin 7 a.v dd analog v dd CC power supply pin to analog block 8 a.v dd analog v dd 9 r.ref r-ch voltage reference CC reference voltage pin. normally connected to a. gnd 10 l.ref l-ch voltage reference through via capacitor to lower impedance 11 l.out l-ch output output left analog signal output pin 12 a.gnd analog gnd CC gnd pin of analog block 13 lrck/wdck left/right clock input when pin 1 is low or leaves open: word clock functions as l-r judgment signal input pin. when pin 1 is high: functions as input data word judgment signal input pin. 14 lrsel/rsi left/right selection input when pin 1 is low or leaves open: r-ch series input functions as pin to select l-r polarity for lrck signal. when lrck signal is high, set lrsel pin to low to input l-ch data; when lrck signal is low, set lrsel pin to high to input l-ch data. when pin 1 is high: functions as r-ch serial data input pin. 15 si/lsi series input input when pin 1 is low or open: l-ch series input functions as l-ch and r-ch serial data input pin alternately. when pin 1 is high: functions as l-ch serial data input pin. 16 clk clock input input pin for read clock of serial input data
m pd6376 5 2. input signal format ? input data must be input as 2s complement, msb first. 2s complement is a method of expressing both positive numbers and negative numbers as binary numbers. see the table below. 2s complement decimal number l.out, r.out pin voltage typ. (v) (msb) (lsb) (reference values) note 0111 1111 1111 1111 +32767 2.6 0111 1111 1111 1110 +32766 0000 0000 0000 0001 +1 0000 0000 0000 0000 0 1.6 1111 1111 1111 1111 C1 1000 0000 0000 0001 C32767 1000 0000 0000 0000 C32768 0.6 note when a.v dd = 5.0 v values differ depending on ic fabrication variations, supply voltage fluctuations, and ambient temperature. ? synchronize the (si, lsi, rsi) data bit delimitations and the lrck, wdck reverse timing to the falling edge of clk. ? clk requires the input of 16 clocks between sample data (16 bits). also, make the time interval for 1 bit the same as 1 clock cycle.
m pd6376 6 2.1 supplying clock to clk even outside sample data interval 2.1.1 serial data input (pin 1 is low or open) synchronize the reverse timing of lrck with the falling edge of clk upon completion of lsb input (point a in figure 2-1 ). figure 2-1 timing chart for serial data input a a interval of 1 sample data lsb clk si lrck 16 1234 1234 5678910111213141516 msb lsb msb 2.1.2. inputting parallel data (pin 1 is high) synchronize the timing of the falling edge of wdck with the falling edge of clk upon completion of lsb input of data (lsi, rsi) (point a in figure 2-2 .). figure 2-2 parallel data input timing chart a a lsb clk lsi rsi wdck 16 1234 12 5678910111213141516 msb lsb msb lsb 16 1234 12 5678910111213141516 msb lsb msb
m pd6376 7 2.2 supplying clock to clk only during sample data interval the analog outputs of the l.out and r.out pins are updated after the input of 4.5 clocks following data input. (see 4. electrical characteristics, timing charts 1 and 2 .) 2.2.1 inputting serial data (pin 1 low or open) place the lrck reverse timing between the falling edge of clk at lsb input completion (point a in figure 2-3 ) and the next msb input start time (point b in figure 2-3 ) (so as to include points a and b). figure 2-3 timing chart of serial data input a ab b 1-sample data interval lrck reverse interval lrck reverse interval lsb clk si lrck 16 1234 1234 5678910111213141516 msb lsb msb 2.2.2 inputting parallel data (pin 1 high) place the wdck falling edge timing between the falling edge of clk at lsb input completion (point a in figure 2-4 ) and the next msb input start time (point b in figure 2-4 ) (so as to include points a and b). place the wdck rising edge timing between the third falling edge of clk from msb input completion (point c in figure 2-4 ) and the falling edge of clk upon lsb input start (point d in figure 2-4 ) (so as to include points c and d). figure 2-4 timing chart of parallel data input a ab bc d wdck falling edge interval wdck falling edge interval wdck rising edge interval lsb clk lsi rsi wdck 16 1234 12 5678910111213141516 msb lsb msb lsb 16 1234 12 5678910111213141516 msb lsb msb
m pd6376 8 3. usage cautions insertion of a muting circuit in the next stage after the m pd6376 is recommended. if no muting circuit is inserted in the next stage, shock noise may be generated when power is applied.
m pd6376 9 4. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol rating unit supply voltage v dd C0.3 to +7.0 v output pin voltage v out C0.3 to v dd +0.3 v logic input voltage v in C0.3 to v dd +0.3 v operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the device reliability may be impaired. the absolute maximum ratings are values that may physically damage the product. be sure to use the product within the ratings. recommended operating range parameter symbol condition min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v logic input voltage (high) v ih 0.7v dd v dd v logic input voltage (low) v il 0 0.3v dd v operating temperature range t a C20 +25 +75 c output load resistance r l r.out or l.out pin 5 k w conversion frequency f s 400 khz clock frequency f clk 10 mhz clock pulse width f sck 40 ns si, lrck set time t dc 12 ns si, lrck hold time t cd 12 ns electrical characteristics (t a = 25 c, v dd = +5 v) parameter symbol condition min. typ. max. unit resolution res 16 bit total harmonic distortion 1 thd 1 f in = 1 khz, 0 db 0.04 0.09 % total harmonic distortion 2 thd 2 f in = 1 khz, C20 db 0.1 0.3 % full-scale output voltage v fs 2.0 2.3 v p-p cross talk c.t 0 db per channel, f in = 1 khz 85 95 db s/n ratio s/n jis-a 96 db dynamic range d.r f in = 1 khz, C60 db 92 db circuit current i dd f in = 1 khz, 0 db 6.0 12 ma
m pd6376 10 timing chart 1 ? when pin 1 is low or open (serial input) 4.5 clocks lsb clk si lrck lrck l.out r.out 16 1 2345678910111213141516 msb lsb n note n 1 234567891011 msb (r-ch) (r-ch) (l-ch) (l-ch) n ?1 n ?1 analog output update note when the lrck signal is high, set the lrsel pin to low to input l-ch data. when the lrck signal is low, set the lrsel pin to h igh to input l-ch data. t sck t sck clk si t cd t dc clk lrck t dc t cd
m pd6376 11 timing chart 2 ? when pin 1 is high (parallel input) t sck t sck clk si t cd t dc clk wdck t dc t cd 4.5 clocks lsb clk lsi rsi wdck l.out r.out 16 1 2345678910111213141516 msb lsb n 1 234567891011 msb n? n lsb 16 1 2345678910111213141516 msb lsb n n + 1 1 234567891011 msb n? n analog output update
m pd6376 12 typical characteristics (t a = 25 c) note 20 khz low-pass filter: 298blr-010n (toko) used thd vs. frequency characteristics thd vs. v dd characteristics 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 frequency f (khz) (?0 db) note f s = 88.2 khz v dd = 5.0 v note f s = 88.2 khz f in = 1 khz, 0 db (full scale) thd (%) 23 5 10 20 voltage gain vs. frequency characteristics 0 ? ?0 0.1 0.2 0.3 0.5 1 frequency f (khz) note f s = 88.2 khz v dd = 5.0 v voltage gain (db) 23 5 10 20 thd vs. r l characteristics 10 1.0 0.1 0.01 100 1 k 10 k 100 k load resistance r l ( w ) note f s = 88.2 khz f in = 1 khz, 0 db v dd = 5.0 v thd (%) 1 m 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0 3.0 4.0 5.0 6.0 7.0 v dd (v) thd (%) thd vs. v out characteristics note f s = 88.2 khz f in = 1 khz v dd = 5.0 v 10.0 5.0 3.0 2.0 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 ?0 ?0 ?0 ?0 ?0 ?0 0 v out (db) thd (%)
m pd6376 13 5. application circuit example (1) f s to 4 f s mode (l/r data serial input mode) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 123 456 78 16 15 14 13 12 11 10 9 384 f s lrck si clk +5 v +5 v +5 v +5 v +5 v +5 v +10 v +10 v op amp. op amp. note +5 v + + + + + + + 0.1 f m m 0.1 f 47 f mm m m m 47 f 10 f 1/2 2/2 22 f m 22 f l-ch out r-ch out 100 k w 100 k w 100 k w 100 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w + 10 f 1000 pf 1000 pf 1000 pf 1000 pf npc sm5807 pd6376gs m note assuming secondary active lpf (gain: k = 2, quality factor: q = 1, cutoff frequency: f c . = . 30 khz) oversampling, the attenuation characteristics are moderate. if oversampling is not performed, use a high-order filter. remark operational amplifier (op amp.): m pc4558 (2) 8 f s mode (l/r data parallel input mode) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 384 f s lrck si clk +5 v +5 v +5 v +5 v +10 v +10 v note +5 v +5 v + + + + + + + 0.1 f m 0.1 f 47 f 47 f m m m m m 10 f 22 f m 22 f m l-ch out r-ch out 100 k w 100 k w 100 k w 100 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w 5.6 k w + 10 f 1000 pf 1000 pf 1000 pf 1000 pf npc sm5813 9 16 15 14 13 12 11 10 12345678 pd6376gs m op amp. 1/2 op amp. 2/2 note secondary active lpf (k = 2, q = 1, f c . = . 30 khz) remark operational amplifier (op amp.): m pc4558
m pd6376 14 6. measuring circuit example +5 v + + + 47 f 47 f 47 f 100 f 100 f 100 f 0.1 f m 0.1 f m m + + + + 2/2 op amp. 2/2 5.6 k w 5.6 k w 5.6 k w 3.6 k w 3.6 k w 5.6 k w v dd pd6376 sampling frequency f s = 88.2 khz 3.6 k w 3.6 k w 100 k w 200 w l r 100 f m m m m + 100 k w 200 w + anritsu mg22a lrck 98 7 6 5 4 3 2 1 10 11 12 13 14 15 16 si clk lpf lpf v ref 298blr-010n (toko) 298blr-010n (toko) (+2.5 v) h.p. 339 a (30 khz lpf on) op amp. 1/2 m m m
m pd6376 15 7. package drawings 16 pin plastic sop (300 mil) item millimeters inches a b c e f g h i j 10.46 max. 1.27 (t.p.) 1.8 max. 1.55 7.7?.3 0.78 max. 0.12 1.1 5.6 m 0.1?.1 n 0.412 max. 0.031 max. 0.004?.004 0.071 max. 0.061 0.303?.012 0.220 0.043 0.005 0.050 (t.p.) p16gm-50-300b-4 p3 3 +7 note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.20 0.008 +0.10 ?.05 l 0.6?.2 0.024 0.10 ? +7 ? 0.004 +0.008 ?.009 +0.004 ?.002 +0.004 ?.003 a c d g p detail of lead end f e b h i l k m m 18 9 16 j n
m pd6376 16 8. recommended soldering conditions the following conditions must be met when performing soldering for the m pd6376. for more detailed information, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than the recommended conditions, please consult with an nec sales representative. surface mount type soldering conditions m pd6376gs: 16-pin plastic sop (300 mil) soldering process soldering conditions symbol infrared reflow peak package temperature: 230 c, time: 30 seconds max. (at 210 c or higher), ir30-00-1 count: once vps peak package temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp-15-00-1 count: once pin partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) CC caution do not use different soldering methods together (except for pin partial heating).
m pd6376 17 [memo]
m pd6376 18 [memo]
m pd6376 19 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
2 m pd6376 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 [memo] the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

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